Monthly Archives: July 2014

libopencm3 bare-metal Vybrid examples

As I wrote yesterday, I’m currently hacking on libopencm3 for bare-metal Vybrid development. This effort advanced quite a bit, the GitHub repository now contains code to use the UART and GPIOs from the Cortex-M4.

The Hardware I use consists of a Toradex Colibri VF61 on a Iris Carrier Board. The code should also run fine on Freescales Vybrid Tower board (TWR-VF65GS10). Currently I use the preinstalled Linux BSP consisting of U-Boot, Linux 3.0 Kernel and a OpenEmbedded based root file system. Read more »

Vybrid bare-metal fun

Freescale Vybrid SoC

Freescale Vybrid SoC

In preparation to my talk at BetterEmbedded I had a deeper look into the second core of Freescales Vybrid VF6xx SoC. I wanted to create a bare-metal test firmware for the Cortex-M4 processor. As the Cortex-M4 is a companion of the Cotex-A5 in the same SoC, its boot process is different compared to a normal Microcontroller (e.g. STM32F4 or similar). Microcontroller usually boot directly from memory mapped NOR flash.

ARM SoCs in general contain a small, internal boot ROM where the cores start from. This boot ROM then tries to boot from different devices, such as NAND or SD-Card. For the Vybrid SoCs normally the Cotex-A5 is the boot CPU, which in my case is running Linux from NAND (the Timesys BSP). On startup, the Cortex-M4 is in an unclocked state and need to be started from the Linux side. With the Timesys BSP, a Vybrid specific kernel module called mcc is provided. This kernel module not only implements the Multi-Core Communication library but also allows to load an image into RAM and start the secondary CPU. The utility mqxboot allows to access this functionality from userspace. This components implement the boot procedure for the Cortex-M4 described in chapter 19.11, “Running Secondary Core”, of the Vybrid Reference Manaul.

The secondary core has not access to a NOR storage as it would have in a microcontroller. Instead the firmware runs completely from RAM. Read more »