The Cortex-M3 has a new assembler instruction SVC to call the supervisor (usually the operating system). The ARM7TDMI used to call this interrupt SWI, but since this interrupt works differently on Cortex-M3, ARM renamed the instruction to make sure people recognize the difference and implement those calls correctly. The machine opcode however is still the same (bits 0-23 are user defined, bits 24-27 are ones).
On the Cortex-M3, other interrupts can interrupt the processor during state saving of the SVC interrupt (late arrival interrupt handling). Those late arriving interrupts most certainly leave the registers corrupted after execution. Therefor we cannot read the parameters form registers r0 to r4 directly as we could on the ARM7TDMI using SWI interrupts. Fortunately, the Cortex-M3 saves all registers used in standard C procedure call specification (ABI) on the stack. So the SVC handler can get the parameters directly from the stack.
Cortex-M3 stack frame